Increased voltage levels and faster switching speeds influence on sensor placement and accuracy in EV systems

The advancements in the EV industry, such as WBG devices and 800 V systems, introduce specific technical challenges for sensor accuracy and physical placement. Higher operational voltages require more robust electromagnetic interference (EMI) filtering, while faster switching speeds generate high dv/dt and di/dt noise.

This FAQ examines how these factors affect sensing integrity and provides strategies for system design.

Q: How does high-voltage EMI filtering affect ac voltage sensing accuracy?
A: In 800 V systems, EMI filtering is necessary to meet regulatory standards. Designers typically implement large Y-capacitors, sometimes reaching 100 nF, between high-voltage lines and protective earth. These components introduce a trade-off regarding ac voltage sensing accuracy due to the time constant they insert into the measurement loop.

Data from Figure 1 identify two primary error mechanisms:

Transient-state settling errors: During a transient event or at the start of a measurement cycle, the Y-capacitor must charge through the sensing resistor. This results in a settling time delay. If the system relies on rapid insulation monitoring, this delay can prevent the sensor from reading the true voltage in a timely manner.
Steady-state phase displacement: Because Y-capacitors have frequency-dependent impedance, they introduce a phase shift. As shown in Figure 1, the sensed voltage waveform leads the true voltage, creating a phase delay that can compromise the accuracy of insulation resistance calculations.

Figure 1. Impact of Y-capacitor parasitic effects on voltage sensing accuracy, demonstrating transient-state settling delays (left) and steady-state phase displacement (right). (Image: Texas Instruments)

To improve accuracy, the resistance in the measurement network should be reduced. Lowering the resistance shortens the charge and discharge periods, which minimizes phase deviation and settling time.

Q: How do high dv/dt nodes dictate the physical placement of sensors?
A: WBG devices, such as SiC MOSFETs, switch at high speeds, generating common-mode noise due to high dv/dt. In these systems, physical placement must account for electromagnetic coupling between power loops and sensitive signal traces.

Figure 2 maps specific high dv/dt switching nodes within bidirectional ac/dc and dc/dc converters. These nodes act as sources of capacitive noise coupling.

Figure 2. Mapping of high dv/dt switching nodes in bidirectional ac/dc and dc/dc converters, identifying primary sources of capacitive noise coupling that dictate sensor placement. (Image: Wolfspeed)

Placement guidelines:

Separation: Sensitive sensing signals, gate loops, and input/output connectors should not be placed near high dv/dt switching nodes.
Shielding: In high-density designs where physical separation is limited, grounded heat sinks can be utilized as physical shields. These shields intercept capacitive noise before it reaches the sensing circuitry.

Q: How can PCB layout geometry mitigate high di/dt magnetic coupling?
A: GaN devices exhibit fast turn-on transients, often exceeding 100 kV/μs, which generate high di/dt changes. These changes cause magnetic coupling that can penetrate sensor isolation barriers. This results in radio frequency interference that rectifies within operational amplifiers, manifesting as a dc shift in the output signal.

Figure 3 provides a comparison of layout techniques:

Figure 3a shows significant current sensor distortion caused by a layout with large, horizontal signal and ground loops.
Figure 3b demonstrates clean waveforms achieved through an optimized physical layout.

Figure 3. Comparison of current sensor outputs: (a) disruptive distortion caused by horizontal ground and signal loops; (b) clean waveforms achieved through a minimized vertical multi-loop layout. (Image: IEEE)

Designers should implement minimized, vertical multi-loop areas. By stacking VCC, signal, and ground traces vertically across the main power board and control board, the system maximizes negative mutual-partial inductance. This effect cancels out the external magnetic coupling from the power switching loop, ensuring measurement integrity despite high di/dt transients.

Summary

Designing for 800 V and WBG architectures requires balancing aggressive EMI filtering with sensor performance. Large Y-capacitors introduce phase displacement and lag that must be mitigated by lowering sensing resistance.

Physical layout is equally important, as designers must isolate sensors from high dv/dt switching nodes or deploy grounded heat sinks for shielding. For high di/dt environments, implementing vertical, tightly stacked PCB multi-loops maximizes negative mutual inductance to cancel magnetic noise.