The MIPI Alliance has released a significant update to its C-PHY interface specification designed for connecting cameras and displays in mobile and mobile-influenced industries. Version 3.0 introduces an 18-Wirestate mode encoding option that increases the maximum performance of a C-PHY lane by approximately 30 to 35 percent, delivering up to 75 Gbps over a short channel to support the growing demands of ultra-high-resolution image sensors.
The new 32b9s encoding option transports 32 bits over nine symbols while maintaining C-PHY’s low EMI and power characteristics. For camera applications, this new mode enables lower symbol rates and lane counts for existing use cases or higher throughput with current lane counts for advanced imaging applications. These include next-generation prosumer video content creation on smartphones, machine vision quality-control systems, and advanced driver assistance systems in automotive environments.
C-PHY supports the MIPI Camera Serial Interface 2 and Display Serial Interface 2 ecosystems in low-power, high-speed applications across mobile, PC compute, and IoT applications. The specification provides efficient throughput with a minimized number of interconnect signals due to its three-phase coding, which reduces system interconnects and electromagnetic emissions. It offers flexibility to reallocate lanes within a link and enables low-latency transitions between high-speed and low-power modes.
The specification includes an alternate low-power feature enabling link operation using only C-PHY’s high-speed signaling levels and an optional fast lane turnaround capability that supports asymmetrical data rates for optimized transfer rates. C-PHY can coexist on the same device pins as MIPI D-PHY, allowing designers to develop dual-mode devices, and it is backward-compatible with previous C-PHY versions to aid implementation.
Development work continues on MIPI D-PHY, with version 3.5 released in 2023, which includes an embedded clock option for display applications. The forthcoming version 3.6 will expand embedded clock support for camera applications targeting PC/client computing platforms. In contrast, version 4.0 will extend embedded clock support for mobile and beyond-mobile machine vision applications and increase data rates beyond 9 Gbps per lane. MIPI Alliance has also documented the longer channel lengths of both C-PHY and D-PHY, demonstrating their usability in larger end products with minimal changes to specifications.
Leave a Reply
You must be logged in to post a comment.