Highlights
-High-quality DesignWare USB 3.1 Device Controller IP reduces integration risk and accelerates availability of USB 3.1 SoCs
-USB 3.1 IP integrators can gain 2X faster data transfer speeds than –USB 3.0 and upgrade to USB 3.1 IP with no changes to existing USB software
-DesignWare USB 3.1 IP Virtual Development Kit helps developers quickly bring-up, enhance and optimize existing software
-Verification IP, written in native SystemVerilog UVM, provides thorough built-in coverage, verification plan and debug to simplify testbench development
-HAPS FPGA-based prototyping system enables hardware/software integration and system validation of USB 3.1 designs
Synopsys, Inc., a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today introduced the industry’s first USB 3.1 IP solution, consisting of DesignWare® USB 3.1 Device Controller, an IP Virtual Development Kit (VDK) and verification IP (VIP) to accelerate the development of high-performance storage, digital office and mobile system-on-chip (SoC) applications. Synopsys’ DesignWare USB 3.1 IP solutions support 10 Gbps data transfer rates, power-down capabilities and compatibility with existing USB 3.0 software stacks and device protocols. Based on the DesignWare USB 3.0 Controller IP architecture, which has shipped in more than 100 million SoCs, the DesignWare USB 3.1 Device Controller IP enables designers to integrate USB 3.1 functionality with significantly less risk and faster time-to-market.
The DesignWare USB 3.1 IP VDK, part of the Synopsys IP Accelerated initiative, helps developers quickly bring-up, enhance and optimize existing software for their specific DesignWare USB 3.1 Device Controller configuration. The IP VDK consists of a reference virtual prototype that includes a processor subsystem reference design, a configurable model of the DesignWare USB 3.1 Controller IP, a Linux® software stack and reference drivers. Software developers can use the IP VDK as a proven target for early software development, bring-up, debug and test in parallel with SoC development. Hardware developers can use the HAPS® FPGA-based prototyping system for hardware/software integration and system validation of USB 3.1 designs, as demonstrated in November 2013.
Synopsys’ USB 3.1 VIP is based on Synopsys’ native SystemVerilog and native UVM architecture, offering ease of integration, high performance, configurability, coverage and debug to speed the protocol verification process. The USB 3.1 VIP supports Verdi Protocol Analyzer, a protocol-centric debug environment that substantially increases user productivity with protocol-aware features to simplify viewing and debug of complex protocols.
Availability
The DesignWare USB 3.1 Device Controller IP and USB 3.1 VIP are available now. The DesignWare USB 3.1 IP Virtual Development Kit is planned to be available in Q1 2015.
Synopsys
www.synopsys.com